1. Field of the Invention
The present invention relates to a signal outputting apparatus suitably used in an image reading apparatus such as an image reader.
2. Related Background Art
A signal outputting apparatus for receiving output signals from a large number of signal sources, time-serially re-arranging or amplifying them, and outputting the re-arranged or amplified signals, often comprises a plurality of integrated circuit chips when the number of signal sources becomes very large.
As an example of a signal outputting apparatus having a plurality of integrated circuit chips, a multi-chip type image sensor is known.
The multi-chip type image sensor is an equal-magnification image sensing unit obtained by adhering a plurality of solid-state image sensor chips on a substrate, and is used in various products such as a facsimile apparatus, scanner, image reader, and the like.
FIG. 13 shows the equivalent circuit of the signal outputting apparatus. The apparatus shown in FIG. 13 comprises three image sensor chips 1 to 3, the output terminals of which are connected to a single output line. Assume that each chip is a linear sensor having two pixels in FIG. 13, for the sake of simplicity. Since these chips have the same configuration, the chip 1 will be exemplified below. The chip 1 comprises photoelectric conversion elements P1 and P2, signal holding capacitors C1 and C2, switch means M1 and M3 inserted between the photoelectric conversion elements and holding capacitors, switch means M2 and M4 inserted between the holding capacitors and an output line L1, a reset means M5 for resetting the output line L1 in the chip, an amplifier means A1, a buffer means B1, and a switch means SW1 inserted between the buffer means and unit output line.
The operation of the unit will be briefly described below. The individual chips simultaneously start photoelectric conversion (photocarrier accumulation), and simultaneously receive ON pulses at terminals TR1 to TR3 after an elapse of a predetermined period of time. In response to the ON pulses, optical signal outputs accumulated on the photoelectric conversion elements P1 to P6 of the three chips are respectively read out to the holding capacitors C1 to C6, thus ending the accumulation.
When scanning circuits operate to time-serially read out signals in the capacitors C1 and C2 first, these signals are voltage-amplified by the amplifier means A1, and the amplified signals are output from an output terminal 51 via the buffer means B1 and switch means SW1.
Upon completion of the output from the first chip, signals of the next chip begin to be output from a terminal 52. Upon completion of the output from the second chip, signals of the third chip are output from a terminal 53. In this way, signals output from the photoelectric conversion elements of the individual chips are sequentially output to a unit output terminal OUT.
The apparatus shown in FIG. 13 comprises the signal holding capacitors C1 and C2 in correspondence with the pixels (P1 and P2). However, in a recent technique disclosed in Japanese Patent Publication No. 8-4127, a plurality of holding capacitors are arranged for one pixel, and store a signal in the dark state of the pixel and an optical signal read out from that pixel. By obtaining a difference signal between these signals using a differential amplifier or the like arranged at the output side, a noise reduction of the signal can be attained.
However, in this signal outputting apparatus, when signals are output from the respective chips onto a common output line 54, the chips may often have different offset voltages between the signal outputs and reference voltage (e.g., ground potential GND).
FIG. 14 shows voltage waveforms for explaining the offset voltages generated in units of chips.
In FIG. 14, signals 55 and 56 are output from the photoelectric conversion elements P1 and P2 of the chip 1, signals 57 and 58 are output from the photoelectric conversion elements P3 and P4 of the chip 2, and signals 59 and 60 are output from the photoelectric conversion elements P5 and P6 of the chip 3.
Ideally, the reference output for the output signal from the chip 1, which serves as the reference potential GND, has a shift of an offset voltage Voff1 from the reference potential GND. Similarly, the chip 2 has a shift of an offset voltage Voff2, and the chip 3 a shift of an offset voltage Voff3.
Since these offset voltages are different from each other (Voff1.noteq.Voff2.noteq.Voff3), the output signals obtained from the photoelectric conversion elements P1 to P6 may become higher or lower than a predetermined value Vi even when the amount of light received remains the same.
Hence, even when the apparatus shown in FIG. 13 reads a solid black image, it may be read the image as a stripe image.
Such offset voltages are produced due to the offset voltages of the photoelectric conversion elements themselves, and the output offset voltages of the amplifier means and buffer means. Especially, the offset voltages produced by the photoelectric conversion elements and amplifier means become larger at the output terminal OUT as the amplifier means has a higher gain.
In the existing integrated circuit manufacturing processes, since the chips obtained have different characteristics albeit slightly, they often have different offset voltages.